Peripheral Component Interconnect (PCI) is the most common used transport interface in computer systems. However, with advancement of computer technologies, the processing speed of central processing units increases substantially, and thereby the transport speed of peripheral devices has to increase as well. Consequently, a Peripheral Component Interconnect Express (PCIE), which is different from PCI, is developed. PCIE transports data serially so that connected devices do not need to share bandwidth. In addition, it also supports hot-plug, which brings considerable convenience for users.
In the PCIE specification, North Bridge chip of a computer system need to connect with coupled PCIE peripheral devices according to PCIE parameters configured in the North Bridge chip when the computer system starts up. The PCIE parameters include power limits, scramble mechanisms, and timing and driving levels of transport signals. Because the PCIE parameters described above are configured in North Bridge chip when they are manufactured, users cannot modify the parameters in accordance with different using requirements and using environments. For example, differences in environmental temperatures influence timing and driving levels of transport signals so that signals cannot be transported securely between North Bridge chip and PCIE peripheral devices. Thereby, performance and stability of PCIE peripheral devices will be affected. Accordingly, in order to enhance performance and stability of PCIE peripheral devices, it is indispensable to modify PCIE parameters in North Bridge chip for re-configuring the PCIE.
In general, parameters in a computer system are modifies in terms of software. However, because North Bridge chip need to connect with connected PCIE peripheral devices when the computer system starts up and the central processing unit is not normal yet, the PCIE parameters can not modified by using software before connection.
Accordingly, it is imperative to provide a method for re-configuring PCIE when a computer system starts up and before North Bridge chip complete connecting with the PCIE peripheral devices.